top of page

ABOUT PEAKSOURCE

Prior to starting PeakSource Analytical I was with the IBM Microelectronics Division in Essex Junction, Vermont for 31 years as an engineer and laboratory manager in semiconductor characterization, fault isolation, analytical technology development, and reliability failure analysis. I am experienced in all facets of micro and nanoelectronic yield and reliability failure analysis with a particular emphasis on fault isolation using magnetic, thermal, photonic, and electron/ion beam techniques. I have performed magnetic microscopy for over eleven years on a wide variety of die, substrate, and package level yield and reliability failures and customer returns and continue to be active in research and development. 
 
Since 2005 I have also provided professional training and technical education to companies and individuals in the U.S., Europe, and Asia for ASM International, CEI Europe, Spyro Technology, and Semitracks, Inc. I am a past general chair and regular contributor to the International Symposium for Testing and Failure Analysis (ISTFA) and other major industry conferences. I am a member of the Electronic Device Failure Analysis Society (EDFAS), a Senior Member of the IEEE, and hold the BSEE degree from the University of New York at Buffalo.

“With decades of experience performing, managing, and teaching fault isolation and failure analysis I know how critical it is to your business to identify the root-cause of failures as quickly and carefully as possible. I welcome the opportunity to use my expertise to help you solve your design, development, manufacturing, quality, and reliability problems."

Selected Publications

 

  • "High-Resolution Backside GMR Magnetic Current Imaging on a Contour-Milled Globally Ultrathin Die," ISTFA, 2014

  • "Enhanced Comparison of Lock-In Thermography and Magnetic Microscopy for 3D Defect Localization of System in Packages," ISTFA, 2012

  • "Localization of Dead Open in a Solder Bump by Space Domain Reflectometry," ISTFA 2012

  • "Fault isolation Challenges and Opportunities for Proximal-probe Imaging," IPFA, 2012

  • "A Comparison of Lock-in Thermography and Magnetic Current Imaging," ISTFA, 2011

  • "Non Destructive Failure Analysis Technique with a Laboratory Based 3D X-ray Nanotomography System," LSIT Japan, 2006

  • "Quantitative Analysis and Depth Measurement via Magnetic Field Imaging," EDFA Magazine, 2005

  • "High Resolution Backside Imaging and Thermography using a Numerical Aperture Increasing Lens," ISTFA, 2003

  • "Scanning SQUID Microscopy for Die Level Fault Isolation," ISTFA, 2002

  • "Failure Analysis Requirements for Nanoelectronics," IEEE Transactions on Nanotechnology, 2002

  • "From Microns to Molecules - Can FA Remain Viable Through the Next Decade?," ISTFA, 2002 (Best conference paper)

  • "Picosecond Imaging Circuit Analysis," IBM Journal of Research and Development, 2000

  • "Failure Analysis of Timing and Iddq -Only Failures from the SEMATECH Test Methods Experiment," IEEE ITC, 1999 (Best conference paper)

  • "Non-Invasive Backside Failure Analysis of Integrated Circuits by Time-Dependent Light Emission: Picosecond Imaging Circuit Analysis," ISTFA, 1998

    (Outstanding paper award)

  • "Finding Fault with Deep-Submicron ICs," IEEE Spectrum Magazine, 1997

  • "Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics," IEEE International Test Conference, 1996

 

US Patents

US 20140124878 A1     Mapping density and temperature of a chip, in situ

7,671,604                         Nanoscale fault isolation and measurement system

7,620,931                         Method of adding fabrication monitors to integrated circuit chips

7,484,423                         Integrated carbon nanotube sensors

7,397,263                         Sensor differentiated fault isolation

7,285,860                         Method and structure for defect monitoring of semiconductor devices using power bus wiring grids

7,239,167                         Utilizing clock shield as defect monitor

7,230,335                         Inspection methods and structures for visualizing and/or detecting specific chip structures

7,194,706                         Designing scan chains with specific parameter sensitivities to identify process defects

7,116,094                         Apparatus and method for transmission and remote sensing of signals from integrated circuit devices

7,089,138                         Canary device for failure analysis

6,650,768                         Using time resolved light emission from VLSI circuit devices for navigation on complex systems

6,452,209                         Semiconductor devices having backside probing capability

6,307,162                         Integrated circuit wiring

6,245,587                         Method for making semiconductor devices having backside probing capability

6,232,143                         Micro probe ring assembly and method of fabrication

6,078,057                         Semiconductor devices having backside probing capability

6,010,392                         Die thinning apparatus 

bottom of page